Universal Serial Bus System Architecture by Don Anderson, MindShare

By Don Anderson, MindShare

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1 Introduction Cache systems are designed to minimize the average access time for memory references. Uniprocessor cache misses can be classified into the three categories: conflict, compulsory, and capacity misses [Hil87]. The number of conflict misses can be reduced by a more associative cache or by the introduction of a victim cache [Jou90]. Larger cache lines and a number of prefetching algorithms have been proposed to reduce compulsory misses, while the conventional approach for reducing capacity misses is simply to increase the size of the cache - a brute force approach often enabled by a manufacturing process shrink.

T. Austin. DIVA: A Reliable Substrate for Deep-Submicron Processor Design. 7. 8. 9. 10. 11. 12. 13. InProceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture, pp. 196~207, Dec. 1999. P. Sweazy and A. J. Smith, A Class of Compatible Cache Consistency Protocols and their Support by the IEEE Futurebus. In Proceedings of the 13th Annual International Symposium on Computer Architecture, pp. 414-423, June 1986. A. Cimatti, E. Clarke, F. Giunchiglia, and M. Roveri, NuSMV: A New Symbolic Model Verifier.

The modeled system consisted of 16 processors connected by a 200 MHz split-transaction address bus and a 16 byte full crossbar for routing data. Each processor had a 1 GHz, 4-way super scalar out-of-order core with split 64 kB 2-way set-associative L1 caches. Main memory latency incurs a 60 ns access time, not including network and arbitration delays. The cache controllers implement an optimized MOESI protocol modeled after the Gigaplane [12]. In the interest of time, we removed the L2 caches and write-buffers from the simulated system.

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