By Bruce Jacob
At the present time, computer-system optimization, at either the and software program degrees, needs to examine the info of the reminiscence method in its research; failing to take action yields platforms which are more and more inefficient as these platforms develop into extra advanced. This lecture seeks to introduce the reader to crucial info of the reminiscence process; it pursuits either computing device scientists and machine engineers in and in academia. approximately conversing, machine scientists are the clients of the reminiscence procedure, and machine engineers are the designers of the reminiscence process. either can gain greatly from a uncomplicated realizing of the way the reminiscence method quite works: the pc scientist may be greater built to create algorithms that practice good, and the pc engineer could be greater outfitted to layout platforms that procedure the optimum, given the source obstacles. at present, there's consensus between structure researchers that the reminiscence approach is "the bottleneck," and this consensus has held for over a decade. just a little inexplicably, many of the learn within the box remains to be directed towards enhancing the CPU to higher tolerate a gradual reminiscence method, in place of addressing the weaknesses of the reminiscence procedure without delay. This lecture may still get the majority of the pc technological know-how and machine engineering inhabitants up the steep a part of the training curve. no longer each CS/CE researcher/developer must do paintings within the reminiscence process, yet, simply as a wood worker can do his task extra successfully if he is aware a bit of structure, and an architect can do his activity extra successfully if he is aware a bit of carpentry, giving the CS/CE worlds greater instinct concerning the reminiscence procedure might actually help them construct larger structures, either software program and undefined.
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Additional info for The memory system you can't avoid it, you can't ignore it, you can't fake it
It may even be more important for memory, because, as you put more cores per CPU socket (the current trend), you need to increase the per-CPU-socket memory footprint, otherwise memory-per-core and thus performance-per-core will drop. Power is a big problem in every segment of the market space. It is a show stopper in some, and a huge annoyance in others. Alleviating the power problem for more “breathing room” simplifies the search for more bandwidth, lower latency, and higher capacity. 2 You cannot quite power manage DDR2 SDRAM devices in a multi-DIMM system in the way Hur & Lin want to; the termination functionality relies on the DLL for accurate timing.
3. 7: The costs of accessing DRAM. This is a two step process: the precharge command initializes the banks sense amplifiers (sets the voltage on the bitlines appropriately), and the activate command reads the row data from the specified storage capacitors into the sense amplifiers. Once the sense amplifiers have read the data, it can be read/written by the memory controller. Precharge and activate together take several tens of nanoseconds; reading or writing takes roughly a nanosecond. Timing values taken from a Micron 2Gb DDR3-1066 part.
So, were one to purchase 16GB DIMMs, the memory system could have 64GB total, not just 8GB, per channel. Factor of eight. How much do these non-commodity DIMMs cost for a factor of eight increase in capacity? Roughly $2000. Two orders of magnitude. Granted, this represents a minority share of the server-memory market—itself a minority share of the general DRAM market—but, even so, why is anyone willing to pay such a price premium? As mentioned, applications over time have increased in size and scope, and with that increase has come an increased need for memory storage.