By Mohit Arora
This booklet highlights the complicated matters, initiatives and talents that has to be mastered by way of an IP clothier, so that it will layout an optimized and strong electronic circuit to resolve an issue. The ideas and methodologies defined can function a bridge among necessities which are recognized to the fashion designer and RTL code that's ultimate final result, lowering considerably the time it takes to transform preliminary rules and ideas into right-first-time silicon. assurance makes a speciality of actual difficulties instead of theoretical suggestions, with an emphasis on layout ideas throughout numerous points of chip-design.
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Additional info for The Art of Hardware Architecture: Design Methods and Techniques for Digital Circuits
39, there are two potential problems when an asynchronous reset signal is de-asserted asynchronous to the clock signal. 1. Violation of reset recovery time. Reset recovery time refers to the time between when reset is de-asserted and the time that the clock signal goes high again. Missing a recovery time can cause signal integrity or metastability problems with the registered data outputs. 2. Reset removal happening in different clock cycles for different sequential elements. When reset removal is asynchronous to the rising clock edge, slight differences in propagation delays in either or both the reset signal and the clock signal can cause some registers or ﬂip-ﬂops to exit the reset state before others.
26 2 Clocks and Resets Fig. 19 Multiplexing logic and clock sources Multiplexed Clocks clock1 D Q D Q D Q clock2 Multiplexing Logic Adding multiplexing logic to the clock signal can lead to some of the problems discussed in the previous sections, but requirements for multiplexed clocks vary widely depending on the application. Clock multiplexing is acceptable if the following criteria are met: s The clock multiplexing logic does not change after initial conﬁguration s The design bypasses functional clock multiplexing logic to select a common clock for testing purposes s Registers are always in reset when the clock switches s A temporarily incorrect response following clock switching has no negative consequences If the design switches clocks on the ﬂy with no reset and the design cannot tolerate a temporarily incorrect response of the chip, then one must use a synchronous design so that there are no timing violations on the registers, no glitches on clock signals, and no race conditions or other logical problems.
28 Data path re-ordering to reduce switching propagation The primary purpose of a reset is to force the SoC into a known state for stable operations. This would avoid the SoC to power on to a random state and get hanged. Once the SoC is built, the need for the SoC to have reset applied is determined by the system, the application of the SoC, and the design of the SoC. A good design guideline is to provide reset to every ﬂip-ﬂop in a SoC whether or not it is required by the system. In some cases, when pipelined ﬂip-ﬂops (shift register ﬂip-ﬂops) are used in high speed applications, reset might be eliminated from some ﬂip-ﬂops to achieve higher performance designs.