By Peter M. Kogge
Makes a speciality of the layout and implementation of 2 sessions of non-von Neumann laptop structure: these designed for practical and logical language computing.
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It may even be more important for memory, because, as you put more cores per CPU socket (the current trend), you need to increase the per-CPU-socket memory footprint, otherwise memory-per-core and thus performance-per-core will drop. Power is a big problem in every segment of the market space. It is a show stopper in some, and a huge annoyance in others. Alleviating the power problem for more “breathing room” simplifies the search for more bandwidth, lower latency, and higher capacity. 2 You cannot quite power manage DDR2 SDRAM devices in a multi-DIMM system in the way Hur & Lin want to; the termination functionality relies on the DLL for accurate timing.
3. 7: The costs of accessing DRAM. This is a two step process: the precharge command initializes the banks sense amplifiers (sets the voltage on the bitlines appropriately), and the activate command reads the row data from the specified storage capacitors into the sense amplifiers. Once the sense amplifiers have read the data, it can be read/written by the memory controller. Precharge and activate together take several tens of nanoseconds; reading or writing takes roughly a nanosecond. Timing values taken from a Micron 2Gb DDR3-1066 part.
So, were one to purchase 16GB DIMMs, the memory system could have 64GB total, not just 8GB, per channel. Factor of eight. How much do these non-commodity DIMMs cost for a factor of eight increase in capacity? Roughly $2000. Two orders of magnitude. Granted, this represents a minority share of the server-memory market—itself a minority share of the general DRAM market—but, even so, why is anyone willing to pay such a price premium? As mentioned, applications over time have increased in size and scope, and with that increase has come an increased need for memory storage.