The Architecture of High Performance Computers by Roland N. Ibbett (auth.)

By Roland N. Ibbett (auth.)

Introduction 1. 1 historic advancements 1 1. 2 recommendations for bettering functionality 2 1. three An Architectural layout instance three 2 directions and Addresses 2. 1 Three-address platforms - The CDC 6600 and 7600 7 2. 2 Two-address platforms - The IBM System/360 and /370 10 2. three One-address structures 12 2. four Zero-address platforms 15 2. five The MU5 guide Set 17 2. 6 evaluating guideline codecs 22 three garage Hierarcbies three. 1 shop Interleaving 26 three. 2 The Atlas Paging method 29 three. three IBM Cache structures 33 three. four The MU5 identify shop 37 three. five facts Transfers within the MU5 garage Hierarchy forty four four Pipelines four. 1 The MU5 basic Operand Unit Pipeline forty nine four. 2 mathematics Pipelines - The TI ASC sixty two four. three The IBM System/360 version ninety one universal information Bus sixty seven five guideline Buffering five. 1 The IBM System/360 version 195 guide Processor seventy two five. 2 guide Buffering in CDC pcs seventy seven five. three The MU5 guideline Buffer Unit eighty two five. four The CRAY-1 guideline Buffers 87 five. five place of the keep watch over element 89 6 Parallel useful devices 6. 1 The CDC 6600 primary Processor ninety five 6. 2 The CDC 7600 valuable Processor 104 6. three functionality a hundred and ten 6 • four The CRA Y-1 112 7 Vector Processors 7. 1 Vector amenities in MU5 126 7. 2 String Operations in MU5 136 7. three The CDC Star-100 142 7. four The CDC CYBER 205 146 7.

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Extra info for The Architecture of High Performance Computers

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If separate hardware units carry out these activities their operations can be overlapped to give an increased rate of completion of instructions. This technique, first introduced in computers such as Atlas and Stretch, has become known as 'pipeline concurrency'. In a pipeline computer several partially completed instructions are in progress concurrently, and although the time to complete any one instruction is still limited by the sum of the times for the various acti vi ties, the rate at which instructions progress through the pipeline is only limited by the time for an individual activity.

The overall average instruction time was higher, but this was due to the effects of control transfer instructions, as we shall see in Chapter 5, and not to store clashes. Thus, by having a store made up of four independent stacks with two-way interleaving of addresses, the execution time of computational instructions was improved by a factor of two. 8 IlS respectively), and the average rate at which this uni t could execute arithmetic operations was weIl matched to the average store accessing rate.

4 The Pipeline Delay Chain Some problems arise as a result of the physical dimensions of the Proeessor and the layout of the platters within it. Thus it is not feasible to locate all registers pertaining to one stage in close proximity either to eaeh other or to the timing eontrol logie. As a resul t, all the registers of one stage eannot be strobed simul taneously, sinee 'far' strobes 54 The Architecture of High Performance Computers would have to be sent out in advance of 'near' strobes by up to 20 ns.

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