Sampling Theory and Methods by M. N. Murthy

By M. N. Murthy

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This is done by properly choosing the frequency ratio and sometimes by injecting a small amount of noise (dither) with the input signal. The exact same precautions apply to measuring DAC distortion with an analog spectrum analyzer. 44 shows the FFT output for an ideal 12-bit ADC. Note that the average value of the noise floor of the FFT is approximately 100 dB below full-scale, but the theoretical SNR of a 12-bit ADC is 74 dB. 43: Effect of ratio of sampling clock to input frequency on SFDR for ideal 12-bit ADC w ww.

1143 MSPS, fc ϭ 71 MHz, and NZ ϭ 18. Now assume that we desire more margin for the antialiasing filter, and we select fs to be 10 MSPS. Solving Eq. 7. 7 to the next lowest integer, giving NZ ϭ 14. Solving Eq. 519 MSPS. 519 MSPS, fc ϭ 71 MHz, and NZ ϭ 14. The above iterative process can also be carried out starting with fs and adjusting the carrier frequency to yield an integer number for NZ. 3 Data Converter AC Errors This section examines the AC errors associated with data converters. Many of the errors and specifications apply equally to ADCs and DACs, while some are more specific to one or the other.

Most ADCs today have a built-in sample-and-hold function, thereby allowing them to process AC signals. This type of ADC is referred to as a sampling ADC. 26. com 26 Chapter 1 the output data can have large errors, depending on the location of the code. Most ADC architectures are subject to this type of error—some more, some less—with the possible exception of Flash converters having well-matched comparators. Assume that the input signal to the encoder is a sinewave with a full-scale amplitude (q2N/2), where q is the weight of 1 LSB.

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