Power Distribution Networks with On-Chip Decoupling by Mikhail Popovich, Andrey Mezhiba, Eby G. Friedman

By Mikhail Popovich, Andrey Mezhiba, Eby G. Friedman

This e-book offers perception into the habit and layout of strength distribution structures for prime velocity, excessive complexity built-in circuits. additionally offered are standards for estimating minimal required on-chip decoupling capacitance. suggestions and algorithms for computer-aided layout of on-chip strength distribution networks also are defined; besides the fact that, the emphasis is on constructing circuit instinct and realizing the foundations that govern the layout and operation of energy distribution platforms.

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400 428 429 446 447 455 456 1 Introduction In July 1958, Jack Kilby of Texas Instruments suggested building all of the components of a circuit completely in silicon [1]. By September 12, 1958, Kilby had built a working model of the first “solid circuit,” the size of a pencil point. A couple of months later in January 1959, Robert Noyce of Fairchild Semiconductor developed a better way to connect the different components of a circuit [2], [3]. ” The first monolithic integrated circuit (IC) was born, where multiple transistors coexisted with passive components on the same physical substrate [4].

Microphotographs of the first IC (Texas Instruments, 1958), the first monolithic IC (Fairchild Semiconductor, 1959), and the recent high performance dual core Montecito microprocessor (Intel Corporation, 2005) are depicted in Fig. 1. In 1960, Jean Hoerni invented the planar process [5]. Later, in 1960, Dawon Kahng and Martin Atalla demonstrated the first silicon based MOSFET [6], followed in 1967 by the first silicon gate MOSFET [7]. These seminal inventions resulted in the explosive growth of today’s multi-billion dollar microelectronics industry.

At the receiver end of the communication line, the output voltage of the transmitter is compared to the power or ground voltage local to the receiver. Spatial variations in the supply voltage create a discrepancy between the power and ground voltage levels at the transmitter and receiver ends of the communication line. The power noise induced uncertainty in these reference voltages degrades the noise margins of the on-chip signals. As the operating speed of integrated circuits rise, crosstalk noise among on-chip signals has increased.

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