By David Culler, Jaswinder Pal Singh, Anoop Gupta Ph.D.
The most fun improvement in parallel laptop structure is the convergence of generally disparate ways on a standard computing device constitution. This e-book explains the forces at the back of this convergence of shared-memory, message-passing, information parallel, and data-driven computing architectures. It then examines the layout concerns which are serious to all parallel structure around the complete variety of recent layout, overlaying facts entry, communique functionality, coordination of cooperative paintings, and proper implementation of precious semantics. It not just describes the and software program concepts for addressing each one of those matters but in addition explores how those recommendations engage within the comparable method. interpreting structure from an application-driven point of view, it offers complete discussions of parallel programming for prime functionality and of workload-driven overview, in accordance with figuring out hardware-software interactions.
- synthesizes a decade of analysis and improvement for working towards engineers, graduate scholars, and researchers in parallel desktop structure, process software program, and purposes development
- presents in-depth software case reports from special effects, computational technology and engineering, and knowledge mining to illustrate sound quantitative evaluate of layout trade-offs
- describes the method of programming for functionality, together with either the architecture-independent and architecture-dependent points, with examples and case-studies
- illustrates bus-based and network-based parallel structures with case stories of greater than a dozen vital advertisement designs
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Additional info for Parallel computer architecture : a hardware/software approach
Early in the microprocesor era the approach was captured in a single chip building block, the Transputer, which was widely touted during its development by INMOS as a revolution in computing. 52 DRAFT: Parallel Computer Architecture 9/10/97 Convergence of Parallel Architectures 101 001 100 000 111 011 110 010 Figure 1-22 Typical structure of an early message passing machines Each node is connected to neighbors in three dimensions via FIFOs. 7) The emphasis on network topology was significantly reduced with the introduction of more general purpose networks, which pipelined the message transfer through each of the routers forming the interconnection network[Bar*94,BoRo89,Dun88,HoMc93,Lei*92,PiRe94,VEi*92].
One important example of such machine is the IBM SP-2, illustrated in Figure 1-23, which is constructed from conventional RS6000 workstations, a scalable network, and a network interface containing a dedicated processor. Another is the Intel Paragon, illustrated in Figure 1-24, which integrates the network interface more tightly to the processors in an SMP nodes, where one of the processors is dedicated to supporting message passing. A processor in a message passing machine can name only the locations in its local memory, and it can name each of the procesors, perhaps by number or by route.
In addition, advances in compiler technology made instruction pipelines more effective. The mid-80s microprocessor-based computers consisted of a small constellation of chips: an integer processing unit, a floating-point unit, a cache controller, and SRAMs for the cache data and tag storage. As chip capacity increased these components were coalesced into a single chip, which reduced the cost of communicating among them. Thus, a single chip contained separate hardware for integer arithmetic, memory operations, branch operations, and floating-point operations.