High-Performance Computing on the Intel® Xeon Phi™: How to by Endong Wang, Qing Zhang, Bo Shen, Guangyong Zhang, Xiaowei

By Endong Wang, Qing Zhang, Bo Shen, Guangyong Zhang, Xiaowei Lu, Qing Wu, Yajuan Wang

The target of this booklet is to provide an explanation for to high-performance computing (HPC) builders tips on how to make the most of the Intel® Xeon Phi™ sequence items successfully. thus, it introduces a few computing grammar, programming expertise and optimization tools for utilizing many-integrated-core (MIC) structures, and likewise deals advice and tips for real use, in line with the authors’ first-hand optimization event.

The fabric is equipped in 3 sections. the 1st part, “Basics of MIC”, introduces the basics of MIC structure and programming, together with the explicit Intel MIC programming surroundings. subsequent, the part on “Performance Optimization” explains normal MIC optimization strategies, that are then illustrated step by step utilizing the classical parallel programming instance of matrix multiplication. eventually, “Project improvement” provides a collection of useful and experience-driven equipment for utilizing parallel computing in software tasks, together with easy methods to confirm if a serial or parallel CPU application is acceptable for MIC and the way to transplant a software onto MIC.

This ebook appeals to 2 major audiences: First, software program builders for HPC purposes – it is going to allow them to totally make the most the MIC structure and therefore in achieving the extraordinary functionality frequently required in organic genetics, clinical imaging, aerospace, meteorology, and different components of HPC. moment, scholars and researchers engaged in parallel and high-performance computing – it's going to advisor them on find out how to push the boundaries of procedure functionality for HPC functions.

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Additional info for High-Performance Computing on the Intel® Xeon Phi™: How to Fully Exploit MIC Architectures

Example text

Prefix decode instructions include: “Fast” instruction of zero latency (for example, 62/c4/c5/REX/0f), “Slow” instructions of two clock-cycles latency, “lock”, “segment”, and “REP”. In addition, if the operating number is integer times 66; the address is integer times 67. 5 x86 Architecture Computing Unit Every MIC core has a x86 architecture scalar processing unit, which can execute standard x86 instructions (for example, EM64T, but not MMX, SSE, or AVX). The x86 computing core can be managed by the U Pipe (Pipe0) and the V Pipe (Pipe1).

Four hardware threads can run parallel at the same time and also cycling in sequence. 3. Instruction decode and launch units: (a) Instruction decode unit: Every cycle reads two instructions (16B) from the code cache and puts the decoded result into the micro-instruction memory uCode. (b) Instruction launch unit: Reads two instructions from the micro-instruction memory and launches them to Pipe0 and Pipe1. 4. Launch pipe: Every MIC core has two separate pipes, Pipe0 and Pipe1. (a) Pipe0: Another name for U Pipe, which can manage VPU computing units and x86 computing units.

Cache miss” handle unit: when the code or data cache misses, this unit triggers and deals with the miss. 11. CRI: the link interface between the inner core and the on-chip ring bus. The MIC core structure is shown in Fig. 5. 6 shows the inner details of the MIC core structure. The following sections discuss different functional units of the MIC core. 2 Hardware Multi-threading To support hardware multi-threading, the MIC coprocessor has features like basic architecture, stream pipe, and cache inner connection.

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