Fault Tolerant Computer Architecture by Daniel J. Sorin

By Daniel J. Sorin

For a few years, so much desktop architects have pursued one fundamental target: functionality. Architects have translated the ever-increasing abundance of ever-faster transistors supplied by way of Moore's legislations into striking raises in functionality. lately, even though, the bounty supplied by way of Moore's legislations has been followed via a number of demanding situations that experience arisen as units became smaller, together with a lessen in dependability because of actual faults. during this publication, we specialize in the dependability problem and the fault tolerance ideas that architects are constructing to beat it. the 2 major reasons of this ebook are to discover the foremost principles in fault-tolerant computing device structure and to offer the present state of the art - over nearly the earlier 10 years - in academia and undefined. desk of Contents: creation / blunders Detection / mistakes restoration / prognosis / Self-Repair / the long run

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They show that this design point outperforms lockstepped redundant cores, by avoiding certain performance penalties inherent in lockstepping. LaFrieda’s DCC technique [36] uses redundant threads on multiple cores, but it removes the need for dedicated hardware channels for the A-thread to communicate its results to the R-thread. DCC uses the existing interconnection network to carry this traffic. One challenge with redundant multithreading on a multicore processor is handling how the threads interact with the memory system.

Patel. Examining ACE Analysis Reliability Estimates Using Fault-Injection. In Proceedings of the 34th Annual International Symposium on Computer Architecture, June 2007. 1250719 [47] C. Weaver, J. Emer, S. S. Mukherjee, and S. K. Reinhardt. Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor. In Proceedings of the 31st Annual International Symposium on Computer Architecture, pp. 264–275, June 2004. 1310780 [48] P. M. Wells, K. Chakraborty, and G. S. Sohi. Adapting to Intermittent Faults in Multicore Systems.

For mission-critical systems that require the error detection capability of NMR, these costs may be unavoidable, but these costs are rarely acceptable for commodity processors. In particular, as modern processors try to extract as much performance as possible for a given energy and power budget, NMR’s power and energy costs are almost certainly impractical. Also, when using NMR, a designer must remember that N times as much hardware is susceptible to N times as many errors, if we assume a constant error rate per unit of hardware.

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