Embedded Firmware Solutions: Development Best Practices for by Vincent Zimmer

By Vincent Zimmer

Embedded Firmware ideas is the appropriate creation and daily-use box guide--for the millions of firmware designers, engineers, architects, managers, and developers--to Intel's new firmware path (including Quark coverage), exhibiting how one can combine Intel® structure designs into their plans. that includes hands-on examples and workouts utilizing Open resource codebases, like Coreboot and EFI improvement package (tianocore) and Chromebook, this is often the 1st ebook that mixes a well timed and thorough review of firmware recommendations for the swiftly evolving embedded surroundings with in-depth assurance of necessities and optimization.

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Sample text

Downloading Intel FSP Now you understand the basic plumbing and interface of Intel FSP. More practice exercises will be provided in later chapters using coreboot and EDK II codebase to show how they integrate Intel FSP, including the handling of input parameters and output parameters. During these exercises, you will need to download a copy of Intel FSP. Here are the steps: 1. Figure out which CPU and Chipset combo you are designing your firmware for. If you are working on a SoC, you need to figure out which SoC family you are using.

TempRamInit As described in the “Sample Boot Flow” section, this FSP API will load the microcode patches, enable the code cache region specified by the host firmware, and set up a temporary stack to be used until the main memory is initialized. There are a couple of input parameters for passing in: the microcode patch base address and its size, and the host firmware code region base address and its size. The microcode patch mechanism built in FSP will try to load the correct microcode patches for the silicon by matching its CPUID and the ID of the patches; if no matching one is found, the API will return an error code.

The following chapters will be walking you through two firmware stacks as examples for carrying out the platform initialization work. info Chapter 3 ■ Intel® Firmware Support Package (Intel® FSP) There is another entry point of Intel FSP that we have not talked about— NotifyPhase. NotifyPhase is an entry point for the host firmware to call back to Intel FSP after PCI bus enumeration and before booting an OS, because there are things to be adjusted, locked down, and cleaned up; as an example, the TSEG register will be locked so that no one can mess it up after booting an OS.

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