By Roopak Sinha, Parthasarathi Roop, Samik Basu
This publication describes an strategy for designing Systems-on-Chip such that the procedure meets certain mathematical standards. The methodologies provided allow embedded structures designers to reuse highbrow estate (IP) blocks from present designs in an effective, trustworthy demeanour, instantly producing right SoCs from a number of, in all probability mismatching, components.
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A structured and unambiguous approach to modelling of interfaces: RMM reports that many times there could be a misunderstanding regarding the functionality, timing or interface issues related to an IP block. We argue that it is possible to separate the functionality from the interface and timing issues using the proposed approach of SKS-based formal modelling. SKSs allow the precise modelling of IP interfaces including the IP clock. • A rigorous approach for system level IP integration and verification: Using boiler plates and SKSs as inputs, we have developed a model checking based IP composition algorithm that is unique as well as scalable.
For example, the APB will usually have a slower bus than the ASB. Usually, these different clocks are rational, or are obtained by dividing the system clock by different integer values. We can capture timing aspects by simply ensuring that the control and data flow of the system is divided into discrete steps (or states) such that each step represents the state of the IP at a different clock edge, or tick. For example, we can assume that the state machine describing the control-data flow of master 1 (Fig.
Finally, a path satisfies ϕ1 U ϕ2 when there exists a state in that path that satisfies ϕ2 and in all state before that ϕ1 is satisfied. For instance, the CTL property EXϕ is satisfied by the set of states which has at least one next state (denoted by π ) which, in turn, belongs to the semantics of ϕ . When a state s in the model M belongs to the semantics of CTL property ϕ , it is denoted by M, s |= ϕ . If the start state (denoted by s0 ) of M belongs to the semantics of the CTL property ϕ , then it is denoted by M |= ϕ .