Computer Architecture Techniques for Power-Efficiency by Stefanos Kaxiras

By Stefanos Kaxiras

Within the previous few years, strength dissipation has develop into an enormous layout constraint, on par with functionality, within the layout of latest desktops. while some time past, the first activity of the pc architect was once to translate advancements in working frequency and transistor count number into functionality, now energy potency needs to be taken under consideration at each step of the layout procedure. whereas for a while, architects were profitable in offering forty% to 50% annual development in processor functionality, expenditures that have been formerly brushed off finally stuck up. the main severe of those expenditures is the inexorable elevate in strength dissipation and gear density in processors. energy dissipation matters have catalyzed new subject components in machine structure, leading to a considerable physique of labor on extra power-efficient architectures. strength dissipation coupled with diminishing functionality earnings, was once additionally the most reason for the swap from single-core to multi-core architectures and a slowdown in frequency bring up. This publication goals to record probably the most vital architectural innovations that have been invented, proposed, and utilized to minimize either dynamic energy and static strength dissipation in processors and reminiscence hierarchies. an important variety of suggestions were proposed for quite a lot of events and this publication synthesizes these innovations by means of targeting their universal features.

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Candidate regions are considered to be loop nests, call sites, called procedures, statement sequences (straight-line code), or even the entire program. Restricting regions to the above programming constructs has the benefit of making the number of DVFS switchings tractable, since the number of times such regions execute can be determined with reasonable accuracy either statically or by profiling. DVFS occurs only on entering and exiting a region. Finally, candidate regions are selected by size, so DVFS switchings occur only for significantly large pieces of code.

Furthermore, the long runtimes of straightforward MILP approaches make their integration into a compiler somewhat undesirable. Work by Xie et al. expanded on these ideas in several ways [229, 230]. First, they expanded the MILP approach by including energy penalties for mode switches, providing a much finer grain of program control, and enabling the use of multiple input data categories to determine optimal settings. In addition, they determined efficient methods for solving the MILP optimization problem with boundable distance from the true optimal solution.

Wu et al. implemented a prototype of this runtime DVFS optimizer (RDO) and integrated it into an industrial-strength dynamic optimization system (a variant of the Intel PIN system [159]). 2. The dynamic optimizer begins by dispatching “cold” code for execution. A monitor determines whether this code is frequently executed. In this case, the RDO optimization is applied along with other conventional performance optimizations of the dynamic optimizer. 3. The first order of business is to determine the “hotness” of functions and first-level loops in main().

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