Compilation Techniques for Reconfigurable Architectures by João M.P. Cardoso, Pedro C. Diniz

By João M.P. Cardoso, Pedro C. Diniz

This booklet describes quite a lot of code adjustments and mapping innovations for compiling courses written in high-level programming languages to reconfigurable architectures. whereas a lot of those variations and mapping recommendations were built within the context of compilation for standard architectures and high-level synthesis, their program to reconfigurable architectures poses an entire new set of demanding situations- quite while concentrating on fine-grained reconfigurable architectures comparable to modern Field-Programmable Gate-Arrays (FPGAs).

Organized in 8 chapters, this ebook offers a beneficial constitution for practitioners and graduate scholars within the region of desktop technology and electric and desktop engineering to successfully map computations to reconfigurable architectures.

Key Features:

  • Introduces the reader to compilation and reconfigurable computing architectures.
  • Presents a number of compiler code variations and mapping concepts concentrating on important programming languages.
  • Allows the reader to bridge the space among the software program compilation and the compilation and synthesis domains.
  • Brings a few compilation concepts jointly into one based resource, and contains consultant examples in their applications.

  • Provides a ancient standpoint on consultant compilation study efforts over the past 15 years.

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Example text

Int A[N_TRIANG], B[N_TRIANG], H[N_TRIANG]; ... for(int i=0; i

We begin by highlighting the specific responsibility of each compilation phase and their interplay. Given their significance in terms of definition of the overall computing architecture, we describe in detail the internal structure of common high-level synthesis and compilation for fine-grained and coarse-grained reconfigurable architectures, respectively. We then illustrate the application of the various compilation and synthesis concepts with examples of the mapping of computations expressed in the C programming language to fine-grained and coarse-grained reconfigurable architectures.

Typically, this synthesis performs the classical steps of allocation, scheduling and binding of low-level operations given the hardware and execution time constraints derived by the application of high-level transformations. The resulting bit-stream configuration (the set of bits that define the hardware design) is to be loaded on the appropriate RPU, which, and depending on the specific features of the RPU, can include classical instructions with a mix of programmable logic definitions. The back-end code generation step outlined here commonly relies on systemlevel abstractions, such as the organization of the overall data streams and storage, and on the existence of a set of primitives for data communication, loading of configurations, and execution synchronization reminiscent to operating systems’ services.

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