By David Seal
This is often the authoritative reference consultant to the ARM RISC structure. Produced by means of the architects which are actively engaged on the ARM specification, the e-book comprises unique information regarding all types of the ARM and Thumb guide units, the reminiscence administration and cache capabilities, in addition to optimized code examples.
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A2-12 Copyright © 1996-2000 ARM Limited. All rights reserved. 6 Exceptions Exceptions are generated by internal and external sources to cause the processor to handle an event, such as an externally generated interrupt or an attempt to execute an undefined instruction. The processor state just before handling the exception must be preserved so that the original program can be resumed when the exception routine has completed. More than one exception can arise at the same time. ARM supports seven types of exception.
For more details of the Q flag, see Chapter A10 Enhanced DSP Extension. In architecture versions prior to version 5, and in non-E variants of architecture version 5 and above, bit of the CPSR and SPSRs should be treated as described in Other bits on page A2-12. 2 The control bits The bottom eight bits of a Program Status Register (PSR), incorporating I, F, T and M[4:0], are known collectively as the control bits. The control bits change when an exception arises and can be altered by software only when the processor is in a privileged mode.
In this model, base register writeback occurred for LDC, LDM, STC and STM instructions, and the base register was unchanged for all other instructions. The Early Abort Model is not valid in ARM architecture versions 3M, 4 and above. Some of these implementations optionally allowed a Late Abort Model to be selected. This is identical to the Base Updated Abort Model. A2-18 Copyright © 1996-2000 ARM Limited. All rights reserved. 6 Interrupt request (IRQ) exception The IRQ exception is generated externally by asserting the IRQ input on the processor.