Architecture Exploration for Embedded Processors with LISA by Andreas Hoffmann

By Andreas Hoffmann

Already this day greater than ninety% of all programmable processors are hired in embedded structures. This quantity is admittedly no longer staggering, considering that during a customary domestic it's possible you'll locate one or computers outfitted with excessive­ of embedded structures, functionality general processors, yet most likely dozens together with digital leisure, family, and telecom units, each one of them built with a number of embedded processors. furthermore, the elec­ tronic elements of upper-class vehicles include simply over 100 professional­ cessors. accordingly, effective embedded processor layout is unquestionably a space worthy . The query arises why programmable processors are so renowned in embed­ ded procedure layout. the reply lies within the indisputable fact that they assist to slender the space among chip ability and clothier productiveness. Embedded processors cores are not anything yet one step additional in the direction of enhanced layout reuse, simply alongside the traces of normal cells in good judgment synthesis and macrocells in RTL synthesis in prior occasions of IC layout. also, programmable processors let emigrate performance from to software program, leading to an excellent enhanced reuse issue in addition to enormously elevated flexibility.

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The language syntax provides a high flexibility to describe the instructionset of various processors, providing architectural originalities, such as single instruction multiple data (SIMD), multiple instruction multiple data (MIMD), and very long instruction word (VLIW) type architectures [119]. g. in the TMS320C6x of Texas Instruments [120], can be easily modeled. g. superscalarity [121]. Based on the work of [83] and [97, 122, 123], which was primarily targeting at retargetable simulation, the language was enhanced to support the complete processor design flow [25].

The specification of non-terminal operations on a higher level in the hierarchy is completed by the referenced terminal operations on the lower levels. 1 shows a sample operation hierarchy. The operation tree starts with the reserved LISA operation main and branches in operation decode. Operations add, sub, mul, and and terminate the branches as leaves of the tree. 1. Operation hierarchy in LISA. Instructions are formed by composing operations. Generally, the designer is free to determine the abstraction level and modularity of his model based on the operations.

1. CORE architecture also serves as a case study for the architecture implementation step using LISA (cf. chapter 6). The resource section comprises four types of objects: • simple resources, such as single registers, buses, flags, and pins as well as vectors hereof such as register files and memories, • pipeline structures for instructions and data-paths, • pipeline registers that resemble the data stored in latches between each pipeline stage, and • memory maps that locate resources in the address space.

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